The present invention relates to an active damping network, and more particularly to an active damping network for damping ringing effects, and more particularly for undershoot in a write circuit for a disk drive.
Disk drives are employed to store large amounts of information in bits encoded on tracks on the disk in a series of logical 1""s and 0""s. These logical 1""s and 0""s are represented in bit cells, which are areas of uniform size along the length of the tracks on the disk. It is desirable that the information bits be encoded on the disk as densely as practical so that a maximum amount of information may be stored. This can be achieved by increasing bit cell density on the disk, namely by reducing the size of bit cells along a particular track, thereby increasing the number of bit cells on the track. Increasing the number of bit cells per track increases the number of bits that can be encoded on each track, and therefore increases the amount of information stored.
Conventionally, logical 1""s are recorded as transitions in magnetic flux on a magnetic disk for a given bit cell, and the absence of a transition indicates a logical 0. These transitions are created by switching the write current polarity through the write head. Transitions representing logical 1""s are preferably placed within each bit cell near the center of the bit cell so that the data frequency (based on bit cell size and rotational speed of the disk) can be accurately locked by a phase-locked loop during recovery of data from the disk and to ensure that bits are not encoded over a bit cell boundary during write operations. As bit cells are more densely packed on the track, placement of the transitions becomes even more important and difficult to precisely control. Thus, transition placement accuracy and bit cell density are two very important parameters in a write circuit for a disk drive.
Due to the inductive nature of a write circuit head and the output capacitances associated with the write circuitry, ringing effects occur in the write current signal which tend to delay the settling of the write current to its final DC value. These ringing effects adversely affect both transition placement and bit cell size concerns. One option when ringing effects are present is to simply wait for the write current to settle to its final DC value and then enable the next transition for encoding a bit. This option means that bit cell duration must be increased to allow time for the write current to settle. While the accuracy of transition placement within bit cells in such a system will not be negatively affected by the ringing of the write current, the density of bit encoding by the write circuit is poor in comparison to desired goals. Another option when ringing effects are present is to switch the write current before it has settled to its final value. This approach maintains acceptable encoding density but results in decreased placement accuracy of bit encoding and hinders subsequent recovery of data from the disk. More particularly, if the write current has not fully settled from a prior transition, switching for the next transition might commence at totally different, uncontrolled, current levels, which results in sporadic placement of transitions in bit cells. Therefore, both options entail undesirable performance trade-offs where ringing effects are present.
One known solution to the ringing problem has been to connect a damping resistor across the terminals of the write head. The resistive damping reduces the settling time for the write current signal flowing through the head. However, resistive damping has several negative effects on the performance of the write circuit. Since some of the write current is diverted through the damping resistor, write current through the head is reduced. To achieve the desired value of write current through the head, more current must be generated to flow through both the head and the damping resistor. More importantly, the damping resistor slows the rise time for write current transitions. This can adversely affect bit cell density. While resistive damping does reduce settling time, the slower rise times may not be acceptable for high performance write circuits. Undershoot may also occur, which could result in loss of saturation of the head media or contribute to the problem of switching from uncontrolled current levels and result in sporadic bit placement in the bit cells.
One way of implementing the resistive impedance is obtained either through the use of capacitors or using MOS transistors in the linear region in series with a resistor across the write driver output. However, this resistive impedance makes the damping circuit vulnerable to IC process variations. In addition, since this type of damping circuit is active throughout the entire duration of the current transition through the head, it dampens the write circuit waveform during the whole duration of the current transition which can limit high-frequency performance. The prior art fails to show a damping circuit which comes into operation only after the current through the head has been switched and, additionally, which has a low process sensitivity.
FIG. 1 illustrates a damping circuit to dampen the write current waveform. When the current switches from the current source transistor 110 to the current source transistor 108, the voltage at node 2 falls to the negative rail and subsequently rises to the DC value. During the transition, feedback through the capacitor 120 causes low resistive impedance to appear at node 2. This low resistive impedance facilitates the damping characteristics. However, the voltage at node 2 rises slowly because of the loading of the low impedance, and since the rate of change of voltage across the head is directly related to the rate of change of slope of the write current, the settling time and rise/fall times will be negatively affected by this approach.
FIG. 2 illustrates another circuit for damping the write current waveform. In this approach, a programmable resistor is added in parallel to the inductive head. The resistor is programmed to have a high value during the rise time and the overshoot time of the write current waveform and have a lower value subsequently. This damping circuit does not come into operation during the rise and overshoot periods. However, this approach may be sensitive to process variations, namely temperature and power supply variations, as the value of the resistor depends heavily on these conditions. Furthermore, such a technique limits the current accuracy through the inductive head since the resistor shunts a portion of the current away from the head.
An active damping assembly is provided for a disk drive write circuit that includes an active damping circuit, a biasing circuit that is used to trigger the active damping circuit that is used in connection with an inductive load of an H-bridge circuit.